Effect of Driver Width Variations on Propagation Delay of Driver-Interconnect-Load System

The performance of VLSI/ULSI chip is becoming less predictable as device dimensions shrinks below the sub-100-nm scale. Process variation is considered to be a major concern in the design of circuits including interconnect pipelines in current deep submicron regime. Process variation results in uncertainties of circuit performances such as propagation delay. The reduced predictability can be attributed to poor control of the physical features of devices and interconnects during the manufacturing process. Variations in these quantities maps to variations in the electrical behavior of circuits. The channel width of MOSFET varies due to changes in drain/source thickness; substrate, polysilicon and implant impurity level; and surface charge. This paper provides a comprehensive analysis of the effect of channel width variation on the propagation delay through driverinterconnect-load (DIL) system. The impact of process induced driver width variations on propagation delay of the circuit is discussed for three different technologies i.e. 130nm, 70nm and 45nm. The comparison of results between these three technologies shows that as device size shrinks, the process variation issues becomes dominant during design cycle and subsequently increases the uncertainty of the delays. General Terms Interconnects, delay, signal, VLSI.